Global approach to timing margins and constraint definition for SoC design, Part 1

The dependence of yield in respect to design margin is depicted in Figure 1. Below a certain level, yield is destined to be 0, because physical phenomena that occur, and may only become evident after the design phase, in real life devices impair the majority of paths. Increasing margin is going to make the design more robust against those phenomena but also is going to increase the cost of design, in terms of area and power consumption of the chip, and for what concerns the design effort needed to complete the design. Above a certain level, the design is simply impossible.